1. Field of the Invention
The present invention relates to solid-state imaging devices such as a CMOS image sensor and imaging apparatuses including the solid-state imaging devices, and, more particularly to a solid-state imaging device and an imaging apparatus that enable high-speed electronic shutter control.
2. Description of the Related Art
Solid-state imaging devises represented by a CMOS image sensor are used in various camera apparatuses, cellular phones, and the like.
The CMOS image sensor includes a pixel area section in which plural pixels having photoelectric conversion sections formed of photodiodes are arrayed on the same semiconductor substrate in two-dimensional directions and a peripheral circuit area formed on the outside of the pixel area section (see JP-A-2008-236634).
The CMOS image sensor has an electronic shutter function for reading out, when a predetermined time elapses after signal charges accumulated in the photoelectric conversion sections are once reset, the signal charges accumulated in the photoelectric conversion sections to control an accumulation period of the signal charges accumulated in the photoelectric conversion sections.
In other words, the CMOS image sensor once resets, with respect to readout timing, signal charges accumulated in the photoelectric conversion sections before a predetermined accumulation period to accumulate and output only signal charges of light made incident during the predetermined accumulation period.
The CMOS image sensor in the past having the electronic shutter function is explained with reference to FIGS. 8 and 9.
As shown in FIG. 8, the CMOS image sensor includes a pixel area section 2, a vertical scanning circuit 3, a column CDS circuit 4, a horizontal scanning circuit 5, an output circuit 6, and a timing generating circuit 7.
In the pixel area section 2, plural pixels respectively having photoelectric conversion sections are arrayed in two-dimensional directions. The pixel area section 2 receives color component lights corresponding to a spectral characteristic of a color filter arranged above the pixel area section 2 and generates pixel signals corresponding to light amounts.
The vertical scanning circuit 3 scans the pixel area section 2 in row units in the vertical direction (in the column direction).
The column CDS circuit 4 captures the pixel signals of the pixel area section 2 in column units and performs CDS processing and other kinds of signal processing.
The horizontal scanning circuit 5 scans the column CDS circuit 4 in the horizontal direction.
The output circuit 6 applies necessary signal processing to the pixel signals transferred from the column CDS circuit 4 and outputs the pixel signals as image signals.
The timing generating circuit 7 synchronizes operation timings of the vertical scanning circuit 3, the column CDS circuit 4, and the horizontal scanning circuit 5.
In the CMOS image sensor of this example, two pixels adjacent to each other in the vertical direction share a reset transistor, an amplification transistor, and a selection transistor.
Photoelectric conversion sections of the adjacent two pixels are respectively denoted by 201A and 201B.
Sources of transfer transistors 202A and 202B corresponding to the photoelectric conversion sections 201A and 201B are respectively connected thereto.
Transfer lines 203A and 203B are connected to gates of the transfer transistors 202A and 202B.
Drains of the transfer transistors 202A and 202B are connected in common and connected to one reset transistor 204.
A floating diffusion FD between the drains of the transfer transistors 202A and 20B and a source of the reset transistor 204 is connected to a gate of one amplification transistor 205.
A drain of the reset transistor 204 and a drain of the amplification transistor 205 are connected to a power supply line 206.
A gate of the reset transistor 204 is connected to a reset line 207.
A source of the amplification transistor 205 is connected to a drain of a selection transistor 208.
A gate of the selection transistor 208 is connected to a selection line 209. A source of the selection transistor 208 is connected to a vertical signal line 210.
The operation of the electronic shutter of the CMOS image sensor is explained below.
Specifically, the operation of a so-called rolling electronic shutter that resets signal charges of pixels while sequentially scanning the pixels in row units in the vertical direction (the column direction) is explained.
In FIG. 8, signs n, n+1, and the like and suffixes n, n+1, and the like affixed to transfer signals Tx indicate addresses of rows in the vertical direction.
Suffixes m, m+1, and the like affixed to reset signals RET are affixed to respectively distinguish the reset signals RET supplied in two pixels units.
In a row of an address n (hereinafter referred to as n line), as shown in FIG. 8, a reset signal RETm output from the vertical scanning circuit 3 is applied to the reset line 207 while being fixed to “H” and a transfer signal Txn is applied from the vertical scanning circuit 3 to the transfer line 203A as a pulse of positive logic.
Then, the transfer transistor 202A and the reset transistor 204 are turned on and reset operation for removing unnecessary charges accumulated in the photoelectric conversion section 201A in the n line and the floating diffusion FD is performed.
When the transfer transistor 202A is turned off because the transfer signal Txn falls to “L” accumulation of photocharges in the photoelectric conversion section 201A is started from that point. In other words, an accumulation period is started.
Operation same as the operation explained above is also performed in an n+1 line, an n+2 line, an n+3 line, and the like. In other words, shutter target addresses are sequentially selected and the electronic shutter operation is performed.